Research Areas within the
Nano-Wafer Level Packaging Program
Integrated Wafer Level Test Bed
The objective is to design and assemble an integrated test bed to demonstrate 100 micron pitch reliable wafer level packaged system. The test bed shall integrate all the above wafer level packaging technologies including the test and burn-in to meet the required mechanical and electrical integrity
The approach would be to integrate all the enabling technologies into a testbed. The proposed specification for 100 micron pitch wafer level packages will be designed into the testbed. The challenges from electrical signal integrity and thermo-mechanical reliability would be addressed in the 100 micron pitch testbed design and development. The testbed is also intended to demonstrate the wafer level packaging materials and processes. The electrical testing will be done in two phases: (1) DC testing, demonstrating the technologies; and (2) functional testing, demonstrating the test features and compatibility of the technology to testing.
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Develop electrical design and simulation methodologies of the test bed to accommodate 100 micron pitch wafer level packages. The design and characterization techniques used at the wafer level interconnects would be extended to the system test bed keeping in mind the 20-50GHz bandwidth goal.
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Exploration and assessment of the thermo-mechanical reliability.
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DC level testing and burn-in integrated into the board. The test strategies developed at the wafer level would be extended to board level testing.
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Design and development of 100 micron board demonstrating the compatibility between the 100 micron pitch wafer and the 100 micron board.