Journey to Nano Wafer Level Packaging
Information technology (IT) is more than a trillion dollar industry. It includes hardware, software, services and applications. Contrary to the perception, the hardware accounts for better than two thirds and the single most important building block of this hardware, of course, is semiconductor devices such as CMOS, Ga -As, Si- Ge, Silicon- on- insulator for a variety of digital, RF, analog and optoelectronic applications. The total worldwide annual market for these devices is about $150 - 200 B. These devices, the technology for which is at the threshold of Nano scale (100nm), are typically fabricated into wafers as big as 300 mm in diameter and are subsequently diced into individual ICs. They are then packaged, tested, and burned into individual IC devices ready to be surface mount bonded onto system level boards. The total number of ICs produced in year 2000 was about 375B units, each packaged at some cost, typically $00.01U.S. per I/O. The total packaging market, which includes IC Packaging as well as system's packaging, is almost as big as the semiconductor market, together accounting for 25% of IT.
The semiconductor industry is racing toward a historic transition-Nano chips with less than 0.1 micron features. The first set of chips should reach production in 2003. Some of these chips will have several hundred million transistors, which require I/Os in excess of 10,000, power in excess of 200 Watts, providing computing speed in terabits per second.
They require Nano packaging. Nano packaging comes at two levels: wafer level and system board level. This Temasek Professorship focuses on wafer level.
A wafer-level package is one in which the die and "package" are fabricated and tested on the wafer prior to singulation. Nano wafer level packaging uses Nano materials and structures to bring about unprecedented advances in electrical, mechanical, and thermal properties in the chip-to-package interconnections.
1. Smallest IC package size as it is a truly chip-size package (CSP).
2. Lowest cost per I/O because the
interconnections are all done at the wafer level in one set of
parallel
steps.
3. Lowest cost of electrical testing as this is done at the wafer level.
4. Lowest burn-in cost as burn-in is done at the wafer level.
5. Eliminates underfilling with organic materials around the solder joint.
6. Enhances electrical performance because of the short interconnections.
The objectives of the proposed research are to lower cost and improve I/O pitch by an order of magnitude and yet support 20-50 GHz digital and RF applications, some of which require power in excess of 200 watts. The barriers to achieving these objectives are many.
They will be overcome by six focus areas of research:
1. Electrical design.
2. Nano and Micro materials.
3. Nano and Micro interconnection processes.
4. Thermo-mechanical design, modelling and analysis.
5. Test and burn-in at wafer level.
6. Integrated testbed that demonstrates a 100 micron pitch wafer level packaging system.
