Nano-Wafer Level Packaging Program

Useful Links and Information

          The overall objectives of the proposed research are to lower cost and improve I/O pitch by an order of magnitude and yet support 20-50 GHz digital and RF applications, some of which require power in excess of 200 watts. The barriers to achieving these objectives are many and will be overcome by the following focus areas of research.

Research Areas Currently Being Pursued:
1. Electrical Design
2. Thermo-Mechanical Design, Modelling and Reliability
3. Wafer Level Interconnect Approaches
4. Nano-Structured Materials and Interconnection Processes
5. Test and Burn-In System
6. Integrated Wafer Level Test Bed

Click on any of the above links for a more detailed description of the research area.